As the integration density of integrated circuit devices continues to increase, it may be increasingly difficult to form small contact holes to an integrated circuit substrate. As shown in FIG. 1a, a contact hole may be formed in an interlayer dielectric layer 4 on an integrated circuit substrate 2 such as a silicon semiconductor substrate, by forming a patterned photoresist layer 6 on the interlayer dielectric layer 4. The photoresist layer is patterned to form an opening 6a therein. The patterned photoresist layer 6 is then used as a mask to etch the interlayer dielectric layer 4 to expose the integrated circuit substrate 2. As shown in FIG. 1b, anisotropic etching is performed to form a contact hole in 4a that can expose the integrated circuit substrate 2. The contact hole may contact a source/drain region of a field effect transistor that is conventionally formed in the integrated circuit substrate 2. The contact hole 4a may then be filled with conductive material to form a contact for an integrated circuit substrate.
Unfortunately, it may be difficult to form contact holes having a diameter that is less than 0.2 .mu.m with the current state of the art of photolithography. As photolithography continues to improve, it still may be difficult to form increasingly smaller contact holes. In particular, when the interlayer dielectric layer 4 is relatively thick, the upper surface thereof may become larger than the opening 6a, due to erosion of the photoresist layer during etching. Accordingly, there continues to be a need for methods of forming small contact holes to an integrated circuit substrate. Such methods may have particular applicability in forming a storage node of an integrated circuit memory device, wherein higher integration levels make it desirable to form smaller contact holes.